What precision (fp16, bf16, fp8) paths does ComfyUI's source assume on AMD GPUs, and which Radeon generations lose bf16?

Problem. Black images or slow output on AMD may come from precision choices; which dtype ComfyUI picks differs by GPU generation. Conditions. ComfyUI commit fb3befd on ROCm. Method. should_use_fp16 returns True for any HIP build (torch.version.hip). should_use_bf16: for archs in the RDNA2-and-older list (gfx1030..gfx1036, gfx1010..1012, gfx906, gfx900, gfx803) bf16 is reported unsupported (returns True only when manual_cast). fp8 compute is assumed (SUPPORT_FP8_OPS) only for gfx1200, gfx1201, gfx950, gfx1170, gfx1171 with torch >= 2.7 and ROCm >= 6.4; gfx942 is excluded with a comment about an error on a nightly. The --fast option fp16_accumulation is allowed on NVIDIA or AMD. Flag help warns --fp16-vae 'might cause black images'. Example. RX 6700 (gfx1031): bf16 is off, fp16 on; try --fp32-vae or keep default if black images appear. Failure modes. fp16 VAE black images; fp8 assumptions off the list fall back to non-fp8 compute. Limitations. Lists reflect a commit; no AMD hardware run. Version/date. Commit fb3befd, 2026-10-23. Curator qualifications: All cited documentation excerpts located on the live pages by curator GET; no video sources. Correction folded 2026-10-24 from C3-B740-02 (curator-reviewed discovery audit): Problem. C3-B730-08 says fp8 compute is assumed (SUPPORT_FP8_OPS) 'only' for gfx1200, gfx1201, gfx950, gfx1170 and gfx1171 with torch >= 2.7 and ROCm >= 6.4, and that other AMD arches fall back to non-fp8 compute. Conditions. ComfyUI commit fb3befd. Method. SUPPORT_FP8_OPS is initialised from the command-line flag --supports-fp8-compute (help: ComfyUI will act as if the device supports fp8 compute); the arch list only sets it automatically on the AMD path. A user can therefore opt in on an arch outside the list; whether such a run is stable is untested (the source comment says gfx942 gave an error on a torch nightly). Failure modes. Forcing the flag on an unlisted arch may error; assuming no override exists. Limitations. Code reading only, no AMD hardware run. Version/date. Commit fb3befd, read 2026-10-23. Limitations: No hardware verification; arch lists will drift. The statement 'fp16 True for HIP' rests on the code position of the torch.version.hip check inside should_use_fp16. Corrected by C3-B740-02; where the correction disagrees, the correction governs. Evidence status: statements located in the cited sources by a correlated desk review (Claude); not executed; not independently reviewed.

{
  "citations": [
    {
      "url": "https://raw.githubusercontent.com/comfyanonymous/ComfyUI/fb3befd168731438f88bc96e0920a538e8649878/comfy/model_management.py",
      "note": "should_use_bf16 AMD block; should_use_fp16 tail; AMD block, fp8; AMD block, fp8; PerformanceFeature block; --fp16-vae help"
    },
    {
      "url": "https://raw.githubusercontent.com/comfyanonymous/ComfyUI/fb3befd168731438f88bc96e0920a538e8649878/comfy/cli_args.py",
      "note": "should_use_bf16 AMD block; should_use_fp16 tail; AMD block, fp8; AMD block, fp8; PerformanceFeature block; --fp16-vae help"
    }
  ]
}